1. Investigate the PTK STAflow.
2. Setup STA environment for wbcdma and run Primetime.
3. Help GC synthesize and formal checking.
4. Check the SD IO pads timing in Z0.
1. Final release td_modem netlist & sdc on July 14, 09
2. Try synthesis for wb_modem with PTK sdc
1. Sign-off STA timing and tape-out Z1 chip
2. Release modem netlist of Y0
2.1 Re-synthesize TDMA domain for feature enhancement
2.2 ECO fix bugs founded in Z0
2.3 ECO add compatible pins as to WB modem
Today base layer of Z1 chip is taped-out to TSMC. The major changes of this chip comparing to Z0 are,
- Fix minor bugs
- Update 926/946 cores
- Improve timing
- Lower power consumption
I have following accomplishments in my work for recent days.
- May 25 - June 5, Lab bring-up support for TD Z0.
- June 3 - June 6, ECO (Revision ID, DDR PHY default configuration) for TD Z1.
- June 3 - Today, Formal check (RTL-to-Netlist, Netlist-to-Netlist) for TD Z1.
- May 15 - Today, Primetime and timing analysis for TD Z1.
Status of TD Z1 is,
- First routing is done.
- Timing is analyzed for first routing netlist & spef.
- Backend guys are working on hold time violation fix.