Bugs
- ITCM, DTCM, and instruction cache memory in Seagull
- RTC default value of DSP L1SRAM
To-do
- Quick metal change for Seagull
- Change RTC default value of DSP L1SRAM, especially for MBIST mode
head 查看文件前几行：head -100 /etc/passwd
tail 查看文件末尾几行：tail -100 /etc/passwd
sed 命令可以用来查看文件中间部分：sed -n "100,200p" /etc/passwd
Question:
I have a complex clocking scheme in which my two clocks have a frequency ratio of 3:2 and only certain edges can be used for launching or capturing data on cross-domain paths. Using the set_multicycle_path command is not adequate to model the launching and capturing edges in my case.
Specifically, I have a 333 MHz clock called clk_333 and a 222 MHz clock called clk_222. These clocks are synchronous to each other, and all data transfers between the two domains occur on the rising edges of each clock (that is, a rising launch edge and a rising capture edge). Data is transferred from the clk_333 domain to the clk_222 domain as well as from the clk_222 domain to the clk_333 domain.
Clock clk_222 launches data and captures data on every cycle, while clock clk_333 skips one launch edge (M2) and one capture edge (M4) every three cycles to match the clk_222 data rate, as shown in the waveform diagram below. Therefore, data transfers occur from M0 to B2 (green arrow), M4 to B0 (purple arrow), B0 to M2 (orange arrow), and B2 to M0 (blue arrow). No data transfers occur from M2 to B2 or from B2 to M4 (red arrows).
How do I model such a complex clocking scheme?
Answer:
The set_multicycle_path command cannot be used to model the clock relationships described above. Instead, generated clocks must be used to implement separate launch and capture edges for each clock domain, and transfers which cannot occur must be treated as false paths. The following set of constraints will model the arrangement described in the waveform diagram above.
create_clock [get_ports CLK1] -name clk_333 -period 3 -waveform {0 1.5}
create_clock [get_ports CLK2] -name clk_222 -period 4.5 -waveform {0 2.25}
create_generated_clock [get_ports CLK1] -name clk_333_launch -source [get_ports CLK1] -edges {1 2 5 6 7} -add
create_generated_clock [get_ports CLK1] -name clk_333_capture -source [get_ports CLK1] -edges {1 2 3 4 7} -add
set_false_path -from [get_clocks clk_333] -to [get_clocks clk_222]
set_false_path -from [get_clocks clk_222] -to [get_clocks clk_333]
set_false_path -to [get_clocks clk_333_launch]
set_false_path -from [get_clocks clk_333_capture]
Moving around
Obviously, you can use the arrow keys to move around on the command line, but there are several other shortcuts: