foreach_in_collection this_design [get_designs *] {
set this_design_name [get_object_name $this_design]
if { ![regexp {foo_} $this_design_name] } {
rename_design $this_design -prefix “foo_” -update_links
}
}
1. Investigate the PTK STAflow.
2. Setup STA environment for wbcdma and run Primetime.
3. Help GC synthesize and formal checking.
4. Check the SD IO pads timing in Z0.
1. Final release td_modem netlist & sdc on July 14, 09
2. Try synthesis for wb_modem with PTK sdc